Optical Metrology Solutions for 10nm Films Process Control Challenges

Controlling thickness and composition of gate stack layers in logic and memory devices is critical to ensure transistor performance meets requirements, especially at 10nm node due to the 3-d geometry of devices and tight process budget. It has become necessary to measure and control each layer in the gate stack before and after dielectric and metal gate deposition sequences. A typical gate stack can have 5-7 layers including the interfacial layer, high-k dielectric, metal gate stack, work function layers, and cap layers. Similarly, PMOS channel strain is controlled using a graded SixGe1-x stack grown epitaxially over fins in the source/drain regions. This graded stack can have 2-4 layers of different thicknesses and Ge concentrations. This paper discusses the benefit of using spectroscopic ellipsometry with multiple angles of incidence to accurately and precisely determine the thickness of individual layers in critical gate layer stacks at various process steps on planar and grating surfaces. We will also show the benefit of using an advanced laser-based ellipsometer, for ultra-precise measurement of the gate interfacial layer oxides.